About me
I am a Ph.D. candidate in the Department of Computer Science and Engineering at Seoul National University. I am a member of the Architecture and Code Optimization (ARC) Lab, advised by Professor Jae W. Lee. I am interested in computer architecture and systems for deep learning. My current research focuses on hardware and software techniques for efficient on-device LLM inference, spanning heterogeneous computing, processing-in-memory, and quantization. I received my BS in Computer Science and Engineering and BA in Economics at Seoul National University in 2020.
News
- Nov. 27th, 2025: Selected as a winner of Qualcomm Innovation Fellowship Korea 2025.
- Jan. 24th, 2025: Selected as a recipient of Encouragement Prize in the 31st Samsung Humantech Paper Awards. (Acceptance Rate: 116/3152=3.7%)
- Nov. 5th, 2024: “FACIL: Flexible DRAM Address Mapping for SoC-PIM Cooperative On-device LLM Inference” was accepted to HPCA’25.
- Sep. 20th, 2022: Presented my first first-authored paper (with Soosung Kim), “A 40nm 5.6TOPS/W 239GOPS/mm² Self-Attention Processor with Sign Random Projection-based Approximation” at ESSCIRC’22.
Publications
MemSOS: OS-Guided Selective Memory Mirroring
Junghoon Kim, Jongheon Jeong, Seokwon Moon, Seong Hoon Seo, Yeonhong Park, Jinkyu Jeong, Nam Sung Kim, Jae W. Lee, The 32nd IEEE International Symposium on High-Performance Computer Architecture (HPCA), January 2026 (To appear).
DP-LLM: Runtime Model Adaptation with Dynamic Layer-wise Precision Assignment
Sangwoo Kwon, Seong Hoon Seo, Jae W. Lee, and Yeonhong Park, The 39th Annual Conference on Neural Information Processing Systems (NeurIPS), December 2025.
FACIL: Flexible DRAM Address Mapping for SoC-PIM Cooperative On-device LLM Inference
Seong Hoon Seo, Junghoon Kim, Donghyun Lee, Seonah Yoo, Seokwon Moon, Yeonhong Park, and Jae W. Lee, The 31st IEEE International Symposium on High-Performance Computer Architecture (HPCA), March 2025.
A 40nm 5.6TOPS/W 239GOPS/mm² Self-Attention Processor with Sign Random Projection-based Approximation
Seong Hoon Seo*, Soosung Kim*, Sung Jun Jung, Sangwoo Kwon, Hyunseung Lee, and Jae W. Lee, The 48th IEEE European Solid-State Circuits Conference (ESSCIRC), September 2022.
ELSA: Hardware-Software Co-design for Efficient, Lightweight Self-Attention Mechanism in Neural Networks
Tae Jun Ham*, Yejin Lee*, Seong Hoon Seo, Soosung Kim, Hyunji Choi, Sung Jun Jung, and Jae W. Lee, The 48th ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2021.
Accelerating Genomic Data Analytics With Composable Hardware Acceleration Framework
Tae Jun Ham, David Bruns-Smith, Brendan Sweeney, Yejin Lee, Seong Hoon Seo, U Gyeong Song, Young H. Oh, Krste Asanovic, Jae W. Lee, and Lisa Wu Wills, IEEE Micro, vol. 41, no. 3, pp. 42-49, 1 May-June 2021.
Special Issue on Top Picks from the 2020 Computer Architecture Conferences
MERCI: Efficient Embedding Reduction on Commodity Hardware via Sub-Query Memoization
Yejin Lee, Seong Hoon Seo, Hyunji Choi, Hyoung Uk Sul, Soosung Kim, Jae W. Lee, and Tae Jun Ham, The 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2021.
Genesis: A Hardware Acceleration Framework for Genomic Data Analysis
Tae Jun Ham, David Bruns-Smith, Brendan Sweeney, Yejin Lee, Seong Hoon Seo, U Gyeong Song, Young H. Oh, Krste Asanovic, Jae W. Lee, and Lisa Wu Wills, The 47th ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2020.
*denotes equal contributions